december 2014 fch190n65f_f085 n-channel superfet ii frfet mosfet ? 2014 fairchild semiconductor corporation fch190n65f_f085 rev. b1 www.fairchildsemi.com 1 fch190n65f_f085 n-channel superfet ii frfet mosfet 650 v, 20.6 a, 190 m features ? typical r ds(on) = 148 m at v gs = 10 v, i d = 10 a ? typical q g(tot) = 63 nc at v gs = 10v, i d = 10 a ? uis capability ? qualified to aec q101 ? rohs compliant description superfet? ii mosfet is fairchild semiconductor?s brand-new high voltage super-junction (sj) mosfet family that is utilizing charge balance technology for outstanding low on-resistance and lower gate charge performance. this technology is tailored to minimize conduction loss , provide superior switching performance, dv/dt rate and higher avalanche energy. consequently superfetii is very well suited for the soft switching and hard switching topologies like high voltage full bridge and half bridge dc-dc, interleaved boost pfc, boost pfc for hev-ev automotive. superfet ii frfet? mosfet?s optimized body diode reverse recovery performance can remove additional component and improve system reliability. application ? automotive on board charger ? automotive dc/dc converter for hev maximum ratings t c = 25c unless otherwise noted symbol parameter ratings units v dss drain to source voltage 650 v v gs gate to source voltage 20 v i d drain current - continuous (v gs =10) (note 1) 20.6 a pulsed drain current see fig 4 a e as s i n g l e p u l s e av a l a n c h e r a t i n g ( n o t e 2 ) 4 0 0 m j dv/dt mosfet dv/dt 100 v/ns peak diode recovery dv/dt (note 3) 50 p d power dissipation 208 w derate above 25 o c1.67w/ o c t j , t stg operating and storage temperature -55 to + 150 o c r jc m a x i m u m t h e r m a l r e s i s t a n c e j u n c t i o n t o c a s e 0 . 6 o c/w r ja maximum thermal resistance junction to ambient (note 4) 40 o c/w package marking and ordering information device marking device package reel size tape width quantity fch190n65f fch190n65f_f085 to-247 - - 30 d g s for ? current ? package ? drawing, ? please ? refer ? to ? the ? fairchild ? web \ site ? at ? https://www.fairchildsemi.com/package \ drawings/to/ to247a03.pdf notes: 1: current is limited by bondwire configuration. 2: starting t j = 25c, l = 50mh, i as = 4a, v dd = 100v during inductor charging and v dd = 0v during time in avalanche. 3: i sd 10a, di/dt 200 a/us, v dd 380v, starting t j = 25c. 4: r ja is the sum of the junction-to-case and case-to-ambient thermal re sistance, where the case therma l reference is defined as the solder mounting surface of the drain pins. r jc is guaranteed by design, while r ja is determined by the board design. the maximum rating presented here is based on mounting on a 1 in 2 pad of 2oz copper. g d s to-247
fch190n65f_f085 n-channel superfet ii frfet mosfet fch190n65f_f085 rev. b1 www.fairchildsemi.com 2 electrical characteristics t j = 25c unless otherwise noted off characteristics on characteristics dynamic characteristics symbol parameter test conditions min typ max units b vdss drain to source breakdown voltage i d = 250 a, v gs = 0v 650 - - v i dss drain to source leakage current v ds = 650v, t j = 25 o c --10 a v gs = 0v t j = 150 o c(note 5) - - 1 ma i gss gate to source leakage current v gs = 20v - - 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a 3.0 - 5.0 v r ds(on) drain to source on resistance i d = 27a, v gs = 10v t j = 25 o c - 148 190 m t j = 150 o c(note 5) - 346 401 m c iss input capacitance v ds = 25v, v gs = 0v, f = 1mhz - 2447 3181 pf c oss output capacitance - 2345 3048 pf c rss reverse transfer capacitance - 131 - pf r g gate resistance f = 1mhz - 0.5 - q g(tot) total gate charge v dd = 380v i d = 10a v gs = 10v -6382nc q g(th) threshold gate charge - 4.3 5.6 nc q gs gate to source gate charge - 12.6 - nc q gd gate to drain ?miller? charge - 28 - nc switching characteristics drain-source diode characteristics notes: 5: the maximum value is specified by design at t j = 150c. product is not tested to this condition in production. t on turn-on time v dd = 380v, i d = 10a, v gs = 10v, r g = 4.7 - 40 100 ns t d(on) turn-on delay time - 25 - ns t r rise time - 14.5 - ns t d(off) turn-off delay time - 64 - ns t f fall time - 5 - ns t off turn-off time - 69 158 ns v sd source to drain diode voltage i sd = 10a, v gs = 0v - - 1.2 v t rr reverse recovery time i f = 10a, di sd /dt = 100a/ s v dd = 520v - 141 - ns q rr reverse recovery charge - 889 - nc
fch190n65f_f085 n-channel superfet ii frfet mosfet fch190n65f_f085 rev. b1 www.fairchildsemi.com 3 typical characteristics figure 1. normalized power dissipation vs. case temperature 0 25 50 75 100 125 150 0.0 0.2 0.4 0.6 0.8 1.0 1.2 power dissipation multiplier t c , case temperature( o c) figure 2. maximum continuous drain current vs. case temperature 25 50 75 100 125 150 0 5 10 15 20 25 v gs = 10v i d , drain current (a) t c , case temperature( o c) figure 3. 10 -5 10 -4 10 -3 10 -2 10 -1 0.01 0.1 1 single pulse d = 0.50 0.20 0.10 0.05 0.02 0.01 normalized thermal impedance, z t jc t, rectangular pulse duration(s) duty cycle - descending order 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t jc x r t jc + t c p dm t 1 t 2 normalized maximum transient thermal impedance figure 4. peak current capability 10 -5 10 -4 10 -3 10 -2 10 -1 10 100 500 v gs = 10v single pulse i dm , peak current (a) t, rectangular pulse duration(s) t c = 25 o c i = i 2 150 - t c 125 for temperatures above 25 o c derate peak current as follows:
fch190n65f_f085 n-channel superfet ii frfet mosfet fch190n65f_f085 rev. b1 www.fairchildsemi.com 4 figure 5. 1 10 100 1000 0.01 0.1 1 10 100 10us 100us 1ms 10ms i d , drain current (a) v ds , drain to source voltage (v) operation in this area may be limited by r ds(on) single pulse t j = max rated t c = 25 o c 100ms forward bias safe operating area figure 6. 345678 0 10 20 30 40 50 60 t j = -55 o c t j = 25 o c t j = 150 o c pulse duration = 80 p s duty cycle = 0.5% max v ds = 20v i d , drain current (a) v gs , gate to source voltage (v) transfer characteristics figure 7. 0.0 0.3 0.6 0.9 1.2 1.5 0.1 1 10 100 200 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) forward diode characteristics figure 8. 03691215 0 10 20 30 40 50 60 70 5v v gs 15v top 10v 8v 7v 6v 5.5v 5v bottom 80 p s pulse width t j = 25 o c i d , drain current (a) v ds , drain to source voltage (v) saturation characteristics figure 9. 0 4 8 12 16 20 0 5 10 15 20 25 30 35 40 80 p s pulse width t j = 150 o c 5v i d , drain current (a) v ds , drain to source voltage (v) v gs 15v top 10v 8v 7v 6v 5.5v 5v bottom saturation characteristics figure 10. 45678910 0 200 400 600 800 1000 i d = 10a pulse duration = 80 p s duty cycle = 0.5% max r ds(on) , drain to source on-resistance ( m : ) v gs , gate to source voltage (v) t j = 25 o c t j = 150 o c r dson vs. gate voltage typical characteristics
fch190n65f_f085 n-channel superfet ii frfet mosfet fch190n65f_f085 rev. b1 www.fairchildsemi.com 5 figure 11. -80 -40 0 40 80 120 160 200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 pulse duration = 80 p s duty cycle = 0.5% max i d = 10a v gs = 10v normalized drain to source on-resistance t j , junction temperature ( o c ) normalized r dson vs. junction temperature figure 12. normalized gate threshold voltage vs. te mperature -80 -40 0 40 80 120 160 200 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 v gs = v ds i d = 250 p a normalized gate threshold voltage t j , junction temperature( o c) figure 13. -75 -50 -25 0 25 50 75 100 125 150 175 0.90 0.95 1.00 1.05 1.10 1.15 i d = 10ma normalized drain to source breakdown voltage t j , junction temperature ( o c) normalized drain to source breakdown voltage vs. junction temperature figure 14. 0.1 1 10 100 1000 0 1 10 100 1000 10000 100000 f = 1mhz v gs = 0v c rss c oss c iss capacitance (pf) v ds , drain to source voltage ( v ) capacitance vs. drain to source voltage figure 15. 0 10203040506070 0 2 4 6 8 10 v ds = 325v v ds = 260v i d = 10a v ds = 390v q g , gate charge(nc) v gs , gate to source voltage(v) gate charge vs. gate to source voltage figure 16. typical characteristics 0 140 280 420 560 700 0 2.4 4.8 7.2 9.6 12.0 e oss , [ p j] v ds , drain to source voltage [v] figure 16. eoss vs. drain to source voltage
fch190n65f_f085 n-channel superfet ii frfet mosfet fch190n65f_f085 rev. b1 www.fairchildsemi.com 6 figure 17. gate charge test circuit & waveform figure 18. resistive switching test circuit & waveforms figure 19. unclamped inductive sw itching test circuit & waveforms v gs v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd 10v v ds r l dut r g v gs v gs v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd 10v v ds r l dut r g v gs v gs v gs i g = const.
fch190n65f_f085 n-channel superfet ii frfet mosfet fch190n65f_f085 rev. b1 www.fairchildsemi.com 7 figure 20. peak diode recovery dv/dt test circuit & waveforms dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- d = gate pulse width gate pulse period --------------------------
fch190n65f_f085 n-channel superfet ii frfet mosfet fch190n65f_f085 rev. b1 www.fairchildsemi.com 8 mechanical dimensions figure 21. to-247, molded, 3-lead, jedec variation ab package drawings are provided as a service to customers c onsidering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor represen- tative to verify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specific ally the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/package-drawings/to/to247a03.pdf
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fch190n65f_f085 rev. b1 www.fairchildsemi.com 9
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